Eduqas A500QS 2.1: Hardware and communication
The free BugBot lessons that teach this point, a robot to try it on, and the past-paper questions that test it.
Lessons that teach it
- A9.1 Hardware, software and the stored program Computer architecture
Internal components, the three buses and their widths, I/O controllers, the stored program concept, and von Neumann against Harvard. - A9.2 The processor and its registers Computer architecture
The ALU, control unit and clock, general-purpose and dedicated registers, and the status flags an 8-bit ALU sets. - A9.3 The fetch-decode-execute cycle in detail Computer architecture
Register transfer notation, the buses at each step, a full register trace, and a stored program that plays notes. - A9.4 Instruction sets and addressing modes Computer architecture
Opcodes, operands and instruction formats; immediate, direct, indirect and indexed addressing. - A9.8 Performance, pipelining and parallel processors Computer architecture
Cores, cache, clock speed, word length and bus widths; pipelining; CISC and RISC; multicore systems and GPUs. - A9.9 Input, output and storage Computer architecture
How barcode readers, cameras, laser printers and RFID work; magnetic, optical and flash storage; RAM, ROM and virtual storage. - A9.10 Project: a processor of your own Computer architecture
Build a von Neumann machine with register transfers, addressing modes, flags and memory-mapped I/O that plays a scale on the robot. - A12.2 Topologies and wireless networks Networks and the web
Physical and logical bus and star; Wi-Fi, SSIDs, WPA2 and CSMA/CA with RTS/CTS.
Try it on a robot
The task from A9.1 Hardware, software and the stored program, running here. Change the program and press Run.
The specification is Eduqas's own document; this page says which of our lessons teach point 2.1 and is not endorsed by the board.